Linear Regression Module
Linear regression determines whether there exists a linear or linear-like relationship between a dependent and an independent variable and if so, what is the extent of linearity. It is very frequently used as a model for data prediction. It takes in a finite number of values and builds a regression line. This line roughly describes the correlation that exists between the data pairs. Now as the number of data pairs accepted becomes large, the model gets more and more accurate. Now, a single value of independent variable may be given to the system which uses the model, thereby developed, to compute the expected value of the dependent variable. As the machine takes in more and more data pairs in the process, the error in prediction reduces
The top-level design specification is provided above. The Linear Regression Module is a mathematical processor that will take in 8-bit data pairs as inputs (Xi, Yi). The circuit provides a READY output to inform the user that it can accept an input pair at the next clock (CLK) edge. This core has been designed to be able to accept one input in every four clock edges which means there is a gap of three clock edges during which it performs the necessary computations to update the regression model. Of course, the user has the freedom to assert a PREDICT signal at any time during the operation. An active high RESET has also been provided to clear the model and start from scratch.
Project Summary :
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In this project, I have written the RTL level design of the 8-bit Linear Regression module. Functional correctness of the module has been tested against the provided test bench (REVISED version) and all three I/O Files. Simulation, Testing and Verification has been performed in ModelSim platform. Resources can be found on my github page.
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Post functional testing of the basic RTL design, some design-level optimizations were carried out. This includes hardware sharing/reuse, power optimizations etc.
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I have synthesized the design using a tsmc 65nm CMOS library in Cadence RTL Compiler environment.
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I have carried out the Layout I.e. Placement and Routing of the design using the same library and a tsmc 65nm LEF. This has been done in Cadence Encounter environment.
Functional Simulation in ModelSim (left) and Synthesis in RTL compiler (right)
Modularity :
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The code has been modularized through the use of separate modules for various functions that could be used as many number of times as required. I have designed a Multiplier module, A Rounder module, an Up-counter module. These modules can be used as many number of times as required and wherever required. Also, the code is written in behavioral style because it is easier and less verbose for this application, rather than the structural style of coding. Therefore, the operations involved in calculating the 4 coefficients for computation, have not been put into separate modules.
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Robustness:
The design has been made to show absolute robustness for all distributions of data pairs. The different kinds of optimizations used does not affect the original accuracy of operation, neither does it cause the circuit to go to some previously unknown state. All exceptions have been handled so as to keep the design more generalized for any kind of use.
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Logic Optimizations:
The design was optimized to obtain some logic level improvement over the original functional code. The following optimizations were carried out:
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The Multiplier in the circuit used in calculating the product and the squares of the sampled inputs were shared into one. This multiplier has been defined in the Multiplier module.
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The calculation of various numerators and denominators were limited to only when predict signal is present. So, in a way, this will save switching power related to unnecessary calculation of bulky values, using multipliers to do that.
Placed and Routed in Cadence Encounter
For codes, a detailed report and more, visit my github repository here